The technology of making interconnections to provide for vias, lines and other recesses in semiconductor chip structures, flat panel displays, and package applications has been developed for many years. For instance, in developing interconnection technology for very-large-scale-integrated (VLSI) structures, aluminum has been utilized as the primary metal source for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum has been the material of choice because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductors have undesirable properties such as a low melting point which limits its use to low temperature processing, possible diffusion into the silicon during annealing which leads to contact and junction failure, and electromigration. Consequently, a number of aluminum alloys have been developed which provided advances over pure aluminum. For instance, U.S. Pat. No. 4,566,177 discloses a conductive layer of an alloy of aluminum containing up to 3% by weight of silicon, copper, nickel, chromium and manganese was developed to improve electromigration resistance. U.S. Pat. No. 3,631,304 discloses aluminum alloys with aluminum oxide which were also used to improve electromigration resistance.
Recently developed ULSI technology has placed more stringent demands on the wiring requirements due to the extremely high circuit densities and faster operating speeds required of such devices. This leads to higher current densities in increasingly smaller conductor lines. As a result, higher conductance wiring is desired which requires either larger cross-section wires for aluminum alloy conductors or a different wiring material that has a higher conductance. The obvious choice in the industry is to develop the latter using pure copper for its desirable high conductivity.
In the formation of ULSI interconnection structures such as vias and lines, copper can be deposited into such recesses to interconnect semiconductor regions or devices located on the same substrate. However, copper is known to have problems at semiconductor device junctions due to its low electromigration resistance. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of ions in the direction of the electron flow. Any diffusion of copper ions into the silicon substrate can cause device failure. In addition, pure copper does not adhere well to oxygen containing dielectrics such as silicon dioxide and polyimide. To fully utilize copper in interconnection technology, the adhesion properties of copper must also be improved.
U.S. Pat. No. 5,130,274, assigned to the common assignee of the present invention, discloses the use of a copper alloy containing an alloying element of less than 2 atomic % by first depositing an alloy into the recess of an interconnection structure and then forming a copper alloy plug and a thin layer of an oxide of the alloying element on the exposed surface of the plug. However, the technique still does not satisfy the more stringent requirements in ULSI structures where critical dimensions of less than 0.5 .mu.m place a considerable burden on thin film chip interconnections. The use of standard Al (Cu) alloy and a silicon dioxide dielectric in a deep-submicron logic circuit wiring structure results in a large circuit delay caused mainly by the wiring connections.
The use of Cu as an alternative material to Al (Cu) in ULSI wiring structures to increase the chip speed has been attempted by others. However, numerous problems are incurred in CU interconnections such as the tendency of Cu to corrode and the fast surface diffusion rates of copper in thin films. It is known that pure Cu has a smaller electromigration activation energy, i.e., 0.5.sup..about. 0.8 eV, than that in Al (Cu) of 0.8.sup..about. 0.9 eV. This implies that the advantage of using Cu for reducing interconnection electromigration failure at chip operating conditions is largely compromised.
A schematic of an enlarged, cross-sectional view of an electronic structure that utilizes conventional interconnections, made of copper alloy is shown in FIG. 1. The electronic structure 10 contains two levels of copper interconnections 12, 16 and one stud level 14 illustrating a copper wiring structure by a Damascene process on a pre-fabricated device 20. The device 20 is built on a semi-conducting substrate 24. As shown in FIG. 1, a typical Damascene level is first fabricated by the deposition of a planar dielectric stack 26. The dielectric stack 26 is then patterned and etched using standard lithographic and dry etch techniques to produce a desired wiring or via pattern. The process is then followed by the metal depositions of a thin adhesion/diffusion liner 18 and copper alloy metallurgy 12 wherein a bottom silicon nitride layer 28 is used as a diffusion barrier that is previously deposited on top of the device 20 to protect against copper diffusion. After the copper alloy interconnection 12 is formed, a top silicon nitride layer 32 is deposited as an etch stop layer for defining the next level copper interconnection 14. After a second level dielectric stack 34 is deposited, a recess for an interconnect is etched into the dielectric layer 34 and the silicon nitride layer 32.
An interlevel copper alloy stud 14 with liner 22 is then deposited by a technique similar to that used in depositing the first level copper alloy interconnection 12. A variety of metal deposition techniques can be used for filling the trench or via. These techniques include a collimated sputtering process, an ion cluster beam process, an electron cyclotron resonance process, a chemical vapor deposition process, an electroless plating process and an electrolytic plating process. Other techniques such as a co-deposition method in which copper and an alloying element are co-deposited can also be used in forming the copper alloys. For instance, such co-deposition methods include co-sputtering, co-plating, co-chemical vapor deposition and co-evaporation. After the completion of the interlevel copper alloy stud 14, another similar process is repeated to form the second level copper interconnection 16 with liner 24 in a third dielectric stack layer 38. An etch stop layer 36 of silicon nitride is utilized between the stud and the second level interconnections. Finally, a top silicon nitride layer 42 is deposited on top of the copper wiring structure 10 for protecting the device from the environment.
Other workers have attempted to use copper alloys in providing enhanced electromigration resistance. For instance, U.S. Pat. No. 5,023,698 teaches copper alloys containing at least one alloying element selected from the group of Al, Be, Cr, Fe, Mg, Ni, Si, Sn and Zn. U.S. Pat. No. 5,077,005 teaches copper alloys containing at least one member selected from In, Cd, Sb, Bi, Ti, Ag, Sn, Pb, Zr and Hf where the weight percent of the alloying element used is between 0.0003 to 0.01. The copper alloys are used in TAB processes and as print circuit board members. U.S. Pat. No. 5,004,520 also teaches copper foil for film carrier application containing at least one alloying element selected from P, Al, Cd, Fe, Mg, Ni, Sn, Ag, Hf, Zn, B, As, Co, In, Mn, Si, Te, Cr and Zn with the alloying element concentrations from 0.03 to 0.5 weight percent. The alloys are used as connecting leads in integrated circuit chip mounting. Furthermore, U.S. Pat. No. 4,749,548 teaches copper alloys containing at least one alloying element selected from Cr, Zr, Li, P, Mg, Si, Al, Zn, Mn, Ni, Sn, Ti, Be, Fe, Co, Y, Ce, La, Nb, W, V, Ta, B, Hf, Mo and C. The alloying elements are used to increase the strength of the copper alloy. U.S. Pat. Nos. 5,243,222 and 5,130,274 teach copper alloys for improved adhesion and formation of diffusion barriers. However, none of these prior work teaches copper alloys that are sufficiently improved for use in ULSI on-chip or off-chip wiring interconnections to meet the electromigration resistance and the adhesion property requirements. Interconnection structures on ULSI devices must provide dense, fully continuous metal wiring in insulator structures with features much less than 0.5 .mu.m in width, and with aspect ratios higher than 1.
It is therefore an object of the present invention to provide an interconnection structure of copper alloy that does not have the drawbacks and shortcomings of conventional copper interconnection structures.
It is another object of the present invention to provide an interconnection structure of a copper alloy that has improved electromigration resistance, adhesion properties and other surface properties.
It is a further object of the present invention to provide an interconnection structure of copper alloy that utilizes a seed layer at the interface between a copper alloy interconnection body and an electronic device it is connected to.
It is another further object of the present invention to provide an interconnection structure of copper alloy by incorporating a copper alloy seed layer sandwiched in between a copper conductor body and an electronic device to which the interconnection is connected.
It is still another object of the present invention to provide an interconnection structure of copper alloy by depositing a copper alloy seed layer prior to the formation of the copper conductor body which contains at least one element of Sn, In, C, Ti, Zr, N, O, Cl or S for improving the electromigration resistance of the interconnection structure.
It is yet another object of the present invention to provide an interconnection structure of copper alloy by depositing a copper alloy seed layer prior to the formation of the copper conductor body which includes at least one element selected from Al, Mg, Be, Ca, Sr, Ba, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, another further object of the present invention to provide an interconnection structure of copper alloy by utilizing a copper alloy seed layer which contains at least one element selected from B, N, P, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Ag, Au, Zn or Cd for improving the surface properties of the interconnection structure.
It is still another further object of the present invention to provide an interconnection system of copper alloy by depositing a metal seed layer sandwiched between a copper conductor body and an electronic device of a metal selected from Ag, Mo, W or Co to improve the copper conductor deposition process.
It is still another further object of the present invention to provide a method for forming an interconnection structure by first depositing a copper alloy seed layer on an electronic device and then forming a copper conductor body on the seed layer such that electromigration resistance corrosion resistance and adhesion of the interconnection structure are improved wherein the seed layer includes copper and at least one element selected from the group consisting of Sn, In, Zr, Ti, C, O, N, Cl and S.